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High Accuracy Ultralow IQ, 300 mA, anyCAP(R) Low Dropout Regulator ADP3333
FEATURES High Accuracy over Line and Load: 0.8% @ 25 C, 1.8% Over Temperature Ultralow Dropout Voltage: 230 mV (Max) @ 300 mA Requires Only C O = 1.0 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: < 1 A 2.6 V to 12 V Supply Range -40 C to +85 C Ambient Temperature Range Ultrasmall 8-Lead MSOP Package APPLICATIONS Cellular Phones PCMCIA Cards Personal Digital Assistants (PDAs) DSP/ASIC Supplies FUNCTIONAL BLOCK DIAGRAM
IN THERMAL PROTECTION Q1 OUT
ADP3333
CC gm
R1
DRIVER SD
R2 BAND GAP REF
GND
GENERAL DESCRIPTION
The ADP3333 is a member of the ADP333x family of precision low dropout (LDO) any CAP voltage regulators. Pin compatible with the MAX8860, the ADP3333 operates with a wider input voltage range of 2.6 V to 12 V and delivers a load current up to 300 mA. ADP3333 stands out from other conventional LDOs with a novel architecture and an enhanced process that enables it to offer performance advantages over its competition. Its patented design requires only a 1.0 F output capacitor for stability. This device is insensitive to output capacitor equivalent series resistance (ESR) and is stable with any good quality capacitor, including ceramic (MLCC) types for spacerestricted applications. The ADP3333 achieves exceptional accuracy of 0.8% at room temperature and 1.8% over temperature, line, and load variations. The dropout voltage of the ADP3333 is only 140 mV (typical) at 300 mA. This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 A. The ADP3333 has ultralow quiescent current, 70 A (typ) in light load situations.
ADP3333
NC VIN CIN 1F SD ON OFF NC = NO CONNECT IN OUT COUT 1F VOUT
GND
Figure 1. Typical Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADP3333-SPECIFICATIONS1 (V
Parameter OUTPUT Voltage Accuracy2 Symbol VOUT
IN
= 6.0 V, CIN = COUT = 1.0 F, TJ = -40 C to +125 C, unless otherwise noted.)
Min 0.8 Typ Max 0.8 Unit %
Condition VIN = VOUTNOM 0.3 V to 12 V IL = 0.1 mA to 300 mA TJ = 25C VIN = VOUTNOM 0.3 V to 12 V IL = 0.1 mA to 300 mA VIN = VOUTNOM 0.3 V to 12 V TJ = 25C IL = 0.1 mA to 300 mA TJ = 25C VOUT = 98% of VOUTNOM IL = 300 mA IL = 200 mA IL = 0.1 mA VIN = VOUTNOM + 1 V f = 10 Hz to 100 kHz, CL = 10 F IL = 300 mA IL = 300 mA IL = 300 mA, TJ = 25C IL = 300 mA, TJ = 85C IL = 200 mA IL = 10 mA IL = 0.1 mA VIN = VOUTNOM - 100 mV IL = 0.1 mA, VIN = VOUTNOM - 100 mV IL = 0.1 mA, TJ = 0C to 125C SD = 0 V, VIN = 12 V ON OFF 0 SD 12 V 0 SD 5 V TJ = 25C, VIN = 12 V TJ = 125C, VIN = 12 V
-1.8 0.04 0.04
+1.8
% mV/V mV/mA
Line Regulation2 Load Regulation Dropout Voltage VDROP
Peak Load Current Output Noise GROUND CURRENT In Regulation
ILDPK VNOISE
140 105 30 600 45
230 185
mV mV mV mA V rms
IGND
In Dropout
IGND
2.0 2.0 1.5 1.4 200 70 70 70 0.01 2.0 0.85 0.8 0.01 0.01
5.5 4.3 3.3 275 100 190 160 1
mA mA mA mA A A A A A V V A A A A
In Shutdown SHUTDOWN Threshold Voltage SD Input Current Output Current in Shutdown
IGNDSD VTHSD ISD IOSD
0.4 7 4.5 1 1
NOTES 1 Application stable with no load. 2 VIN = 2.6 V for models with V OUTNOM 2.3 V. Specifications subject to change without notice.
-2-
REV. A
ADP3333
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
OUT 1 IN 2
8
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . . -0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . . -40C to +85C Operating Junction Temperature Range . . . . -40C to +125C JA (4-Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W JA (2-Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C/W Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
NC SD
ADP3333
7
TOP VIEW GND 3 (Not to Scale) 6 NC NC* 4
5
NC
NC = NO CONNECT *CAN BE CONNECTED TO ANY OTHER PIN.
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4-6, 8 7
Mnemonic OUT IN GND NC SD
Function Output of the Regulator. Bypass to ground with a 1.0 F or larger capacitor. Input Pin. Bypass to ground with a 1.0 F or larger capacitor. Ground Pin. No Connect. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin.
ORDERING GUIDE
Model ADP3333ARM-1.5-RL ADP3333ARM-1.5-RL7 ADP3333ARM-1.8-RL ADP3333ARM-1.8-RL7 ADP3333ARM-2.5-RL ADP3333ARM-2.5-RL7 ADP3333ARM-2.77-RL ADP3333ARM-2.77-R7 ADP3333ARM-3-REEL ADP3333-3-REEL7 ADP3333ARM-3.15-RL ADP3333ARM-3.15-R7 ADP3333ARM-3.3-RL ADP3333ARM-5-REEL ADP3333-5-REEL7
Output Voltage (V) 1.5 1.5 1.8 1.8 2.5 2.5 2.77 2.77 3 3 3.15 3.15 3.3 5 5
Package Option RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8)
Branding LKA LKA LKB LKB LKC LKC LKD LKD LKE LKE LKF LKF LKG LKH LKH
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3333 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
-3-
ADP3333 -Typical Performance Characteristics
2.502 0mA 2.500
2.502
VOUT = 2.5V
140
2.500
VIN = 6V VOUT = 2.5V
IL = 100 A 120
VOUT = 2.5V
2.498 100mA 2.496 2.494 200mA 2.492 300mA 2.490 2.488 3 4 5 6 8 7 9 10 INPUT VOLTAGE - V 11 12
2.498 2.496 2.494 2.492 2.490 2.488 0 50 150 250 200 100 OUTPUT LOAD - mA 300
GROUND CURRENT - A
OUTPUT VOLTAGE - V
OUTPUT VOLTAGE - V
100 80 60 40 20 0 IL = 0
0
2
4 6 8 INPUT VOLTAGE - V
10
12
TPC 1. Line Regulation Output Voltage vs. Supply Voltage
TPC 2. Output Voltage vs. Load Current
TPC 3. Ground Current vs. Supply Voltage
2.5 VIN = 6V GROUND CURRENT - mA 2.0
OUTPUT CHANGE - %
GROUND CURRENT - mA
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3
3.5
0
VIN = 6V 3.0 IL = 300mA 2.5 2.0 1.5 1.0 0.5 IL = 200mA IL = 100mA
200mA
1.5
1.0
300mA
0.5
0 0 50 100 150 200 OUTPUT LOAD - mA 250 300
-0.4 -50
0 -25 0 25 50 75 100 JUNCTION TEMPERATURE - C 125
IL = 0mA 0 -50 -25 0 25 50 75 100 125
JUNCTION TEMPERATURE - C
TPC 4. Ground Current vs. Load Current
TPC 5. Output Voltage Variation % vs. Junction Temperature
TPC 6. Ground Current vs. Junction Temperature
0.16
INPUT/OUTPUT VOLTAGE - mV
0.14
INPUT/OUTPUT VOLTAGE - V
VOUT - V
0.12 0.10 0.08 0.06 0.04 0.02 0
3.0 2.5 2.0 1.5
VOUT = 2.5V SD = VIN RL = 8.3
3 2 1 0
COUT = 1 F
COUT = 10 F
VIN - V
1.0 0.5 0 1 2 3 TIME - Sec 4
4 2 0 200 400 600 TIME - s VOUT = 2.5V SD = VIN RL = 8.3 800
0
50
100 150 200 OUTPUT LOAD - mA
250
300
TPC 7. Dropout Voltage vs. Output Current
TPC 8. Power-Up/Power-Down
TPC 9. Power-Up Response
-4-
REV. A
ADP3333
2.52
VOUT - V
2.51 2.50 2.49
VOUT - V
VOUT = 2.5V RL = 8.3 CL = 1 F
2.52 2.51 2.50 2.49
VOUT = 2.5V RL = 8.3 CL = 10 F
V
2.7 2.6 2.5 2.4 300
VIN = 4V VOUT = 2.5V CL = 1 F
VIN - V
VIN - V
3.00 40 80 140 TIME - s 180
3.00 40 80 140 TIME - s 180
mA
3.50
3.50
10 200 400 600 TIME - s 800
TPC 10. Line Transient Response
TPC 11. Line Transient Response
TPC 12. Load Transient Response
2.7 2.6
VIN = 4V VOUT = 2.5V CL = 10 F
3 1F
VOUT
2.5
2 1 0 10 F 1F 2 0 200 400 600 TIME - s
10 F
V
2.5 2.4
V
0 3 2 VIN = 6V
300
mA
10 200 400 TIME - s 600 800
0 VIN = 6V 200 400 600 TIME - s 800
VSD
1
VIN = 6V VOUT = 2.5V RL = 8.3
A
800
TPC 13. Load Transient Response
TPC 14. Short-Circuit Current
TPC 15. Turn ON-Turn OFF Response
-20 -30
RIPPLE REJECTION - dB
120
100
VOUT = 2.2V CL = 1 F IL = 500mA CL = 1 F IL = 50 A
VOLTAGE NOISE SPECTRAL DENSITY - V/ Hz
CL = 10 F IL = 500mA
RMS NOISE - V
VOUT = 2.5V IL = 1mA CL = 10 F CL = 1 F
100
10
-40 -50 -60 -70 -80 -90 10 100
80
1
60 300mA 40 0mA
0.1
CL = 10 F IL = 50 A 1k 10k 100k FREQUENCY - Hz 1M 10M
0.01
20 0 0 10 20 30 CL - F 40 50
0.001 10
100
1k 10k 100k FREQUENCY - Hz
1M
TPC 16. Power Supply Ripple Rejection
TPC 17. RMS Noise vs. CL (10 Hz to 100 kHz)
TPC 18. Output Noise Density
REV. A
-5-
ADP3333
THEORY OF OPERATION
The new anyCAP LDO ADP3333 uses a single control loop for regulation and reference functions (see Figure 2). The output voltage is sensed by a resistive voltage divider consisting of R1 and R2 that is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier.
INPUT Q1 COMPENSATION CAPACITOR NONINVERTING WIDEBAND DRIVER gm PTAT VOS R4 OUTPUT ATTENUATION (VBAND GAP /V OUT) R3 D1 FB PTAT CURRENT R2 (a) RLOAD
designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. With the ADP3333 anyCAP LDO, this is no longer true. This device can be used with virtually any good quality capacitor, with no constraint on the minimum ESR. Its innovative design allows the circuit to be stable with just a small 1 F capacitor on the output. Additional advantages of the pole splitting scheme include superior line noise rejection and very high regulator gain, which leads to excellent line and load regulation. An impressive 1.8% accuracy is guaranteed over line, load, and temperature. Additional features of the circuit include current limit and thermal shutdown.
R1 CLOAD
APPLICATION INFORMATION Capacitor Selection Output Capacitor
ADP3333
GND
Figure 2. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature-proportional input offset voltage that is repeatable and very well controlled. The temperature proportional offset voltage is combined with the complementary diode voltage to form a virtual band gap voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources and leads to a low noise design. The R1, R2 divider is chosen in the same ratio as the band gap voltage to the output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from base current loading in conventional circuits is avoided. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. Moreover, the ESR value required to keep conventional LDOs stable changes depending on load and temperature. These ESR limitations make
The stability and transient response of the LDO is a function of the output capacitor. The ADP3333 is stable with a wide range of capacitor values, types, and ESR (anyCAP). A capacitor as low as 1.0 F is all that is needed for stability; larger capacitors can be used if high current surges on the output are anticipated. The ADP3333 is stable with extremely low ESR capacitors (ESR 0), such as multilayer ceramic capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types falls below the minimum overtemperature or with dc voltage. Ensure that the capacitor provides at least 1.0 F of capacitance over temperature and dc bias.
Input Bypass Capacitor
An input bypass capacitor is not strictly required but is recommended in any application involving long input wires or high source impedance. Connecting a 1.0 F capacitor from the input to ground reduces the circuit's sensitivity to PC board layout and input transients. If a larger output capacitor is necessary, then a larger value input capacitor is also recommended.
Output Current Limit
The ADP3333 is short-circuit protected by limiting the pass transistor's base drive current. The maximum output current is limited to about 1 A (TPC 14).
Thermal Overload Protection
The ADP3333 is protected against damage due to excessive power dissipation by its thermal overload protection circuit. Thermal protection limits the die temperature to a maximum of 165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where the die temperature starts to rise above 165C, the output current will be reduced until the die temperature has dropped to a safe level. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, the device's power dissipation should be externally limited so that the junction temperature will not exceed 125C.
-6-
REV. A
ADP3333
Calculating Junction Temperature Printed Circuit Board Layout Considerations
Device power dissipation is calculated as follows PD = (VIN - VOUT ) I LOAD + (VIN ) IGND Where ILOAD and IGND are load current and ground current, and VIN and VOUT are the input and output voltages, respectively. Assuming the worst-case operating conditions are ILOAD = 300 mA, IGND = 2.6 mA, VIN = 4.0 V, and VOUT = 3.0 V, the device power dissipation is PD = (4.0 V - 3.0 V ) 300 mA + (4.0 V ) 2.0 mA = 308 mW The package used on the ADP3333 has a thermal resistance of 158C/W for 4-layer boards. The junction temperature rise above ambient will be approximately equal to
T JA = 0.308 W x 158C /W = 48.7C
Use the following general guidelines when designing printed circuit boards:
* * * * * *
Keep the output capacitor as close to the output and ground pins as possible. Keep the input capacitor as close to the input and ground pins as possible. PC board traces with larger cross sectional areas will remove more heat from the ADP3333. For optimum heat transfer, specify thick copper and use wide traces. Connect the NC pins (4, 5, 6, and 8) to ground for better thermal performance. The thermal resistance can be decreased by approximately 10% by adding a few square centimeters of copper area to the lands connected to the pins of the LDO. Use additional copper layers or planes to reduce the thermal resistance. Again, connecting the other layers to the ground and NC pins of the ADP3333 is best but not necessary. When connecting the ground pad to other layers, use multiple vias.
So, to limit the junction temperature to 125C, the maximum allowable ambient temperature is
T A( MAX ) = 125C - 48.7C = 76.3C
Shutdown Mode
Applying a high signal to the shutdown pin, or connecting it to the input pin, will turn the output ON. Pulling the shutdown pin to 0.3 V or below, or connecting it to ground, will turn the output OFF. In shutdown mode, the quiescent current is reduced to less than 1 A.
REV. A
-7-
ADP3333
OUTLINE DIMENSIONS 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
3.00 BSC
8
5
3.00 BSC
1 4
4.90 BSC
PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Revision History
Location 8/03--Data Sheet changed from REV. 0 to REV. A Page
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated Output Capacitor section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Updated Calculating Junction Temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
-8-
REV. A
C02615-0-8/03(A)

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